Counter ICs

A Shift Register is a sequential logic device made up of a cascade of flip-flops, through which a sequence of bits are ’shifted’. These devices are commonly used to convert between serial and parallel interfaces.

How it works – basic example

In a Shift Register the output of each flip-flop is connected to the input of the next flip-flop in the cascade. With each cycle of the connected clock, the bits are ’shifted’ down the cascade by one flip-flop.

A simple analogy to understand the basic theory or operation would be to consider a glass tube with an opening both ends, and placing a ball marked ’0’ or ’1’ into one end of the tube at a regular intervals.

As each ball is placed into the tube, all the balls are ’shifted’ along by one position. The sequence in which the balls marked ’0’ and ’1’ where fed in is preserved. Also each time one ball is fed in, the ball that has been in the cascade the longest drops out. So if the tube can contain 4 balls at any one time, this could be described as a 4-bit Shift Register.

Common Types of Shift Register

• Serial-in serial-out (SISO) – In this type of Shift Register, the data input and output is serial. With each clock cycle a new bit is fed into the cascade, with the bit furthest along the cascade exiting as an output. So in a 4-bit register, the output trails the input by 4 clock cycles. This matches the simple example above, with the ball that exits the tube being the output.

• Serial-in parallel-out (SIPO) – In this configuration data is converted from serial into parallel format. As described for the SISO variant above, data is fed in serially and shifted down the cascade, the difference is that each flip-flop has an output, allowing the entire bit array to be output simultaneously as a parallel output. This may be done using a latched of buffered output.

• Parallel-in serial-out (PISO) – This variant takes a parallel input and converts into a serial output. To do this the shift register must implement a write/shift sequence. The parallel data input is (written) into each flip-flop of the array simultaneously in one clock cycle, then for the next cycles the register goes into shift mode as the bits are shifted down the flip-flop cascade, being output as serial data. The process then repeats.

• Parallel-in parallel-out (PIPO) – This type of register differs slightly from the others in that inputs and outputs of each flip-flop in the array are not interconnected. Each flip-flop takes one bit of the parallel input, stores it for a cycle, and then outputs the data simultaneously with the other flip-flops in the register, creating a parallel output that matches the input. Like the SISO type above, PIPO variants can be used to temporarily store data, or act a time delay device.

• Universal Shift Register – A configurable Shift Register that can be programmed to act as a SISO, SIPO, PISO or PIPO device, often on the fly.

Read more Read less


Viewing 681 - 683 of 683 products
Results per page
Description Price Package Type Logic Function Number of Stages Logic Family Mounting Type Counter Type Operation Mode Number of Elements Pin Count Minimum Operating Supply Voltage Maximum Operating Supply Voltage Dimensions Length Width
RS Stock No. 443-104
Mfr. Part No.SN74HC166N
PDIP Shift Register 8 HC Through Hole - Parallel to Serial, Serial 1 16 2 V 6 V 19.3 x 6.35 x 4.57mm 19.3mm 6.35mm
RS Stock No. 178-6969
Mfr. Part No.74HC4060D,652
Each (In a Tube of 50)
SOIC Counter 14 HC Surface Mount Binary Up Counter 1 16 2 V 6 V 10 x 4 x 1.45mm 10mm 4mm
RS Stock No. 663-0332
Mfr. Part No.CD74HC4040M
Each (In a Pack of 5)
SOIC Counter 12 HC Surface Mount Binary Up Counter 1 16 2 V 6 V 9.9 x 3.91 x 1.58mm 9.9mm 3.91mm
Related Products
Texas Instruments range of Counters and Shift Registers ...
Texas Instruments range of Counters and Shift Registers from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of ...