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Digilent 410-346-20 Arty Z7-20 APSoC Zynq-7000 Development Board

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Arty Z7 Zynq-7000 Development Board

The Arty Z7-20 is a development platform designed around the Xilinx Zynq-7000™ All Programmable System-on-Chip (AP SoC). The Zynq-7000 architecture integrates a dual-core, 650MHz ARM Cortex-A9 processor with Artix-7 series FPGA logic. This pairing surrounds a powerful processor with a unique set of software defined peripherals and controllers. The Vivado, Petalinux, and SDSoC toolsets each provide a path between defining your custom peripheral set and bringing its functionality up to a Linux OS or 'bare-metal' program running on the processor.

Xilinx Zynq-7000 (XC7Z020-1CLG400C)

• Processor: 650MHz dual ARM Cortex-A9 core
• Look-up Tables (LUTs): 53200
• Flip-flops: 106400
• Block RAM: 630KB
• Clock Management Tiles: 4
• Available Shield I/O: 49
• DDR3 memory controller with 8 x DMA channels and 4 x AXI3 Slave ports
• High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
• Low-bandwidth peripheral controller: SPI, UART, CAN, I²C
• Programmable from JTAG, Quad-SPI Flash or microSD card
• Programmable logic equivalent to Artix-7 FPGA Memory

Board Memory and Power

• On-board IS43TR16256A-125KBL 512MB DDR3 SDRAM with 16-bit bus @ 1050Mbps
• On-board S25FL128S 16MB Quad-SPI Flash with 48-bit unique EUI-48/64™ compatible identifier
• microSD card slot
• Powered from USB or +7V to +15Vdc via barrel jack

System Connectivity

• 10/100/1000 Ethernet via RJ45 connector
• USB-UART Bridge via micro-B socket
• USB-JTAG Programming via micro-B socket
• USB OTG PHY (supports Host only) via USB-A socket

Audio and Video

• HDMI sink port (input)
• HDMI source port (output)
• PWM driven mono audio output via 3.5mm jack socket

Switches and LEDs

• Reset and Program pushbuttons
• 4 x User pushbuttons
• 2 x User slide-switches
• 4 x User LEDs
• 2 x User RGB LEDs

Expansion Connectors

• chipKIT/Arduino R3 Shield headers
• 2 x Standard 12-pin Pmod™ connectors

An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.

Kit NameArty Z7-20 APSoC Zynq-7000
Kit ClassificationDevelopment Board