Renesas Electronics 9DB633AGILF Clock Buffer 28-Pin TSSOP
- RS Stock No.:
- 263-7988
- Mfr. Part No.:
- 9DB633AGILF
- Brand:
- Renesas Electronics
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Subtotal (1 unit)*
$10.23
(exc. GST)
$11.76
(inc. GST)
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Units | Per unit |
|---|---|
| 1 - 9 | $10.23 |
| 10 - 24 | $9.20 |
| 25 - 49 | $9.00 |
| 50 - 99 | $8.70 |
| 100 + | $7.54 |
*price indicative
- RS Stock No.:
- 263-7988
- Mfr. Part No.:
- 9DB633AGILF
- Brand:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 110MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Number of Outputs | 6 | |
| Minimum Supply Voltage | 3.3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Length | 9.8mm | |
| Height | 1.2mm | |
| Width | 4.5 mm | |
| Series | 9DB633 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 110MHz | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 28 | ||
Number of Outputs 6 | ||
Minimum Supply Voltage 3.3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Length 9.8mm | ||
Height 1.2mm | ||
Width 4.5 mm | ||
Series 9DB633 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
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