Renesas Electronics 2305A-1DCG8 Clock Buffer 8-Pin SOIC
- RS Stock No.:
- 264-3451P
- Mfr. Part No.:
- 2305A-1DCG8
- Brand:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
View bulk pricing optionsSubtotal 50 units (supplied on a continuous strip)*
$114.10
(exc. GST)
$131.20
(inc. GST)
Spend over $80.00 ex GST for FREE delivery
Temporarily out of stock
- Shipping from 03 June 2027
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit |
|---|---|
| 50 - 95 | $2.282 |
| 100 - 245 | $1.86 |
| 250 - 995 | $1.744 |
| 1000 + | $1.21 |
*price indicative
- RS Stock No.:
- 264-3451P
- Mfr. Part No.:
- 2305A-1DCG8
- Brand:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | IDT2305A | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series IDT2305A | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
The Renesas Electronics high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133 MHz.
Phase-lock loop clock distribution
Distributes one clock input to one bank of five outputs
Power down mode
Available in SOIC package
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