Renesas Electronics 85104AGILF Clock Buffer, 20-Pin 4 TSSOP
- RS Stock No.:
- 216-6210
- Mfr. Part No.:
- 85104AGILF
- Brand:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
Subtotal (1 unit)*
$41.81
(exc. GST)
$48.08
(inc. GST)
FREE delivery for orders over $60.00 ex GST
Last RS stock
- Final 222 unit(s), ready to ship from another location
Units | Per unit |
|---|---|
| 1 - 18 | $41.81 |
| 19 - 36 | $40.77 |
| 37 + | $40.16 |
*price indicative
- RS Stock No.:
- 216-6210
- Mfr. Part No.:
- 85104AGILF
- Brand:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Series | 85104A | |
| Height | 1mm | |
| Length | 6.5mm | |
| Width | 4.4 mm | |
| Number of Outputs | 4 | |
| Maximum Output Frequency | 700MHz | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Series 85104A | ||
Height 1mm | ||
Length 6.5mm | ||
Width 4.4 mm | ||
Number of Outputs 4 | ||
Maximum Output Frequency 700MHz | ||
Automotive Standard No | ||
The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Four 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)