STMicroelectronics, 32 bit ARM Cortex A7, ARM Cortex M4, STM32MP1 Microcontroller, 650 MHz FLASH, 448-Pin LFBG
- RS Stock No.:
- 193-5397P
- Mfr. Part No.:
- STM32MP157AAA3
- Brand:
- STMicroelectronics
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- 413 unit(s) ready to ship from another location
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Units | Per unit |
|---|---|
| 21 - 41 | $37.20 |
| 42 + | $36.62 |
*price indicative
- RS Stock No.:
- 193-5397P
- Mfr. Part No.:
- STM32MP157AAA3
- Brand:
- STMicroelectronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | STMicroelectronics | |
| Product Type | Microcontroller | |
| Series | STM32MP1 | |
| Package Type | LFBG | |
| Mount Type | Surface | |
| Pin Count | 448 | |
| Device Core | ARM Cortex A7, ARM Cortex M4 | |
| Data Bus Width | 32bit | |
| Maximum Clock Frequency | 650MHz | |
| RAM Size | 256kB | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Number of Programmable I/Os | 176 | |
| DACs | 2 x 12 Bit | |
| Maximum Operating Temperature | 125°C | |
| Height | 1.32mm | |
| Length | 18.15mm | |
| Standards/Approvals | No | |
| Width | 18.15mm | |
| Minimum Supply Voltage | 1.71V | |
| Program Memory Type | FLASH | |
| Number of Timers | 29 | |
| Instruction Set Architecture | RISC | |
| Automotive Standard | No | |
| ADCs | 2 x 16 Bit | |
| Select all | ||
|---|---|---|
Brand STMicroelectronics | ||
Product Type Microcontroller | ||
Series STM32MP1 | ||
Package Type LFBG | ||
Mount Type Surface | ||
Pin Count 448 | ||
Device Core ARM Cortex A7, ARM Cortex M4 | ||
Data Bus Width 32bit | ||
Maximum Clock Frequency 650MHz | ||
RAM Size 256kB | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Number of Programmable I/Os 176 | ||
DACs 2 x 12 Bit | ||
Maximum Operating Temperature 125°C | ||
Height 1.32mm | ||
Length 18.15mm | ||
Standards/Approvals No | ||
Width 18.15mm | ||
Minimum Supply Voltage 1.71V | ||
Program Memory Type FLASH | ||
Number of Timers 29 | ||
Instruction Set Architecture RISC | ||
Automotive Standard No | ||
ADCs 2 x 16 Bit | ||
The STM32MP157A devices are based on the high-performance dual-core Arm® Cortex®- A7 32-bit RISC core operating at up to 650 MHz. The Cortex-A7 processor includes a 32- Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other lowpower embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and CortexA17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA®4 AXI bus interface.
The STM32MP157A devices also embed a Cortex® -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions and data types. The Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32MP157A devices also embed a 3D graphic processing unit (Vivante® - OpenGL® ES 2.0) running at up to 533 MHz, with performances up to 26 Mtriangle/s, 133 Mpixel/s.
The STM32MP157A devices provide an external SDRAM Interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.
The STM32MP157A devices incorporate high-speed embedded memories with 708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus Matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access.
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