STMicroelectronics STM32MP231DAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xA/D 16 bit 64 Bit, ARM V8-M,
- RS Stock No.:
- 482-983
- Mfr. Part No.:
- STM32MP231DAJ3
- Brand:
- STMicroelectronics
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- RS Stock No.:
- 482-983
- Mfr. Part No.:
- STM32MP231DAJ3
- Brand:
- STMicroelectronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | STMicroelectronics | |
| Product Type | Microprocessor | |
| Series | STM32MP23xA/D | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | 64 Bit, ARM V8-M, Arm Cortex | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet | |
| Package Type | TFBGA361 | |
| Minimum Supply Voltage | 1.71V | |
| Pin Count | 361 | |
| Maximum Supply Voltage | 3.6V | |
| Standards/Approvals | JEDEC | |
| Automotive Standard | No | |
| Number of Cores | 2 | |
| Select all | ||
|---|---|---|
Brand STMicroelectronics | ||
Product Type Microprocessor | ||
Series STM32MP23xA/D | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture 64 Bit, ARM V8-M, Arm Cortex | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet | ||
Package Type TFBGA361 | ||
Minimum Supply Voltage 1.71V | ||
Pin Count 361 | ||
Maximum Supply Voltage 3.6V | ||
Standards/Approvals JEDEC | ||
Automotive Standard No | ||
Number of Cores 2 | ||
- COO (Country of Origin):
- TW
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Four I2Cs
Three I3Cs
Four USARTs and three UARTs
One low power UART
Low power consumption
Clock management
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