Microchip AT91SAM9CN12B-CFUR ARM926EJ-S Microprocessor AT91SAM9CN12B 32 bit ARM 400 MHz 217-Pin BGA
- RS Stock No.:
- 775-368
- Mfr. Part No.:
- AT91SAM9CN12B-CFUR
- Brand:
- Microchip
N
Subtotal (1 reel of 1000 units)*
$18,189.00
(exc. GST)
$20,917.00
(inc. GST)
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Units | Per unit | Per Reel* |
|---|---|---|
| 1000 + | $18.189 | $18,189.00 |
*price indicative
- RS Stock No.:
- 775-368
- Mfr. Part No.:
- AT91SAM9CN12B-CFUR
- Brand:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Series | AT91SAM9CN12B | |
| Product Type | Microprocessor | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | NAND | |
| Mount Type | Surface Mount | |
| Minimum Supply Voltage | 0.9V | |
| Package Type | BGA | |
| Maximum Supply Voltage | 1.1V | |
| Pin Count | 217 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Automotive Standard | No | |
| Number of Cores | 1 | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Series AT91SAM9CN12B | ||
Product Type Microprocessor | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type NAND | ||
Mount Type Surface Mount | ||
Minimum Supply Voltage 0.9V | ||
Package Type BGA | ||
Maximum Supply Voltage 1.1V | ||
Pin Count 217 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Automotive Standard No | ||
Number of Cores 1 | ||
- COO (Country of Origin):
- CN
The Microchip processor offers a robust performance for embedded applications, combining Advanced ARM architecture with efficient memory management. It's is designed to enhance multitasking capabilities while ensuring low power consumption.
Supports both 32-bit ARM and 16-bit Thumb instruction sets for performance optimization
Includes a Memory Management Unit for effective address translation and management
Features separate instruction and data buses for improved data throughput
Provides flexible cache configurations, enabling tailored performance for diverse applications
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