Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP
- RS Stock No.:
- 263-7981
- Mfr. Part No.:
- 9DB106BGLF
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal (1 pack of 2 units)*
$16.21
(exc. GST)
$18.642
(inc. GST)
FREE delivery for orders over $60.00 ex GST
In Stock
- Plus 130 unit(s) shipping from 22 December 2025
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Units | Per unit | Per Pack* |
|---|---|---|
| 2 - 8 | $8.105 | $16.21 |
| 10 - 18 | $7.27 | $14.54 |
| 20 - 48 | $7.125 | $14.25 |
| 50 - 98 | $6.875 | $13.75 |
| 100 + | $5.96 | $11.92 |
*price indicative
- RS Stock No.:
- 263-7981
- Mfr. Part No.:
- 9DB106BGLF
- Brand:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Elements per Chip | 5 | |
| Maximum Supply Current | 5 μA | |
| Maximum Input Frequency | 105MHz | |
| Mounting Type | SMD | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Elements per Chip 5 | ||
Maximum Supply Current 5 μA | ||
Maximum Input Frequency 105MHz | ||
Mounting Type SMD | ||
Package Type TSSOP | ||
Pin Count 28 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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